Interested to Buy Any Domain ? << Click Here >> for more details...
verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.
- 2 Answers
- 32099 Views
- Cosmic Circuits, HP, I also Faced
- E-Mail Answers
Answer Posted / chakrapani
if vgs made more means more electronics are attraced to the
channel region so pinch off occures at large valves of vds
| Is This Answer Correct ? | 3 Yes | 7 No |
Post New Answer View All Answers
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
How about voltage source?
What is threshold voltage?
What are the various regions of operation of mosfet? How are those regions used?
What is the difference between nmos and pmos technologies?
How can you model a SRAM at RTL Level?
What are the main issues associated with multiprocessor caches and how might you solve them?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Explain the working of 4-bit Up/down Counter?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Insights of a 4bit adder/Sub Circuit?
Explain what is the depletion region?
What is the difference between the mealy and moore state machine?
Implement a 2 I/P and gate using Tran gates?
Explain Basic Stuff related to Perl?
