Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / kantha
LVS- LAYOUT VERSUS SHEMATIC TEST FROM NETLIST DESIGN
(NORMALLY MANUAL METHOD)
DRC-DESIGN RULE CHECK(EX SPICE TOOL WILL GENERATE ERRORS IF
YOUR DESIGN NOT MET THE STANDARD DESIGN RULES)
| Is This Answer Correct ? | 9 Yes | 16 No |
Post New Answer View All Answers
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What are the steps required to solve setup and hold violations in vlsi?
Describe the various effects of scaling?
What is the main function of metastability in vsdl?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
What are the different measures that are required to achieve the design for better yield?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
What are the different design constraints occur in the synthesis phase?
What are the steps involved in preventing the metastability?
