Answer Posted / rakesh

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DFlip_Flop is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end DFlip_Flop;

Architecture of DFlip_Flop is

begin

---ANother way of writing code for creating D_Flip_Flop in VHDL

process(Clk, Rst)
begin
if (Rst ='1') then
Q <= '0';
elsif(clk='1' and clk'event) then
Q <= D;
end if;
end process;

end ;

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