verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.
Answer Posted / arpan
1. NMOS passes good logic 0 and bad logic 1.
We know the current conduction takes place when the channel
is formed i.e when Vgs > Vt(Threshold voltage). In normal
operation suppose Vg = 5v and Vs = 0v and Vt = 1v.
Fot the above mentioned case Vgs=Vg-Vs
=5v which is
grater than threshold voltage and logic 0 will easily pass.
Now if we want to pass logic 1, we have to make Vs=Vdd
(Suppose 5v). In this case Vgs=0v which is less than
threshold voltage, thus channel is not formed. And a bad
logic 1 is passed.
2. PMOS passes good logic 1 and bad logic 0
For normal operation suppose Vg = 0v and Vs = 5v
and Vt= -1v(threshold voltage for PMOS is -ve). So, Vgs =
-5v. So gate yo source voltage is more -ve and thus channel
will easily form, and logic 1 is passed easily. Now, suppose
Vs= 0v then Vgs=0v. Which is not -ve compare to Vt of PMOS,
thus channel will not form and will pass bad logic 0.
Refer pg 66 of Weste Harris
Is This Answer Correct ? | 67 Yes | 7 No |
Post New Answer View All Answers
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Why does the present vlsi circuits use mosfets instead of bjts?
Explain how binary number can give a signal or convert into a digital signal?
Mention what are three regions of operation of mosfet and how are they used?
Cross section of a PMOS transistor?
Draw the Layout of an Inverter?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Tell me how MOSFET works.
What is Body Effect?
Draw a CMOS Inverter. Explain its transfer characteristics
What are the steps required to solve setup and hold violations in vlsi?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
Basic Stuff related to Perl?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Design an 8 is to 3 encoder using 4 is to encoder?