Answer Posted / arpan

Setup time is the min time before the active edge of the
clock that the data gets stable. If the setup time is
violated then the logic enters into a metastable state. We
can say that setup time is violated when the logic is too
slow compare to clock. So, whenever we do simulations we do
setup time calculation in worst case. Since, in worst case
data changes too late. So, if the design passes the worst
case setup time, then its proper.
Hold time is the min time after the active edge of the clock
that the data should remain stable. Logic will also enter
into the metastable state if hold time is violated. We can
say hold violation occurs when the logic is too fast. So,
whenever we do simulation for hold time calculation we do in
best case since in best case data is changed too early. So,
if the design passes best case hold time, then its proper.

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