Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What?s the difference between Testing & Verification?

Answer Posted / john

Testing is the process of identifying defects in a product.
Verification is the process of ensuring that the product
complies with its specification. Validation is the process
of ensuring that the product meets the users' needs.
Although linked, these are obviously separate. A product may
be defect free but not what was specified or needed; it may
have defects and be not as specified, but may still meet
user need; it may meet specification, but have defects and
not meet the users' need (probably the most common outcome
of software projects!).

Is This Answer Correct ?    30 Yes 2 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What are the different gates where boolean logic are applicable?

1046


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1439


Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1088


Explain why is the number of gate inputs to cmos gates usually limited to four?

1489


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3853


Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1189


Draw a 6-T SRAM Cell and explain the Read and Write operations

1274


What transistor level design tools are you proficient with? What types of designs were they used on?

5056


what is Slack?

1167


Are you familiar with the term snooping?

3493


Explain about 6-T XOR gate?

1240


Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1111


What does it mean “the channel is pinched off”?

1343


What is the function of enhancement mode transistor?

1096


Explain the working of 4-bit Up/down Counter?

4425