Answer Posted / eric
This is caused because the device dimensions have been scaled down, but power supply and the operating voltages have not scaled accordingly. This causes the increase of electrical field strength and the velocity of electrons. Electrons trapped in oxide change the threshold voltage, typically increasing the threshold of NMOS, decreasing the threshold of PMOS. The hot-electron phenomenon can lead to a long-term reliability problem. To keep the hot-carrier effect under control, specailly engineered drain and source regions are used to keep the electrical fields in bound.
| Is This Answer Correct ? | 4 Yes | 1 No |
Post New Answer View All Answers
What is Noise Margin? Explain the procedure to determine Noise Margin?
What is the difference between nmos and pmos technologies?
what is multiplexer?
what is Slack?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
For CMOS logic, give the various techniques you know to minimize power consumption
why is the number of gate inputs to CMOS gates usually limited to four?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
Explain depletion region.
Implement a 2 I/P and gate using Tran gates?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
If not into production, how far did you follow the design and why did not you see it into production?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
How does a Bandgap Voltage reference work?
Describe the various effects of scaling?
