Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF
VLSI CIRCUIT?

Answer Posted / bhanu kiran kumar

verification is to verify functionality of the design where as testing is to find manufacturing faults.

Is This Answer Correct ?    22 Yes 2 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Insights of a 4bit adder/Sub Circuit?

3424


What transistor level design tools are you proficient with? What types of designs were they used on?

5110


what is SCR (Silicon Controlled Rectifier)?

1101


Are you familiar with the term snooping?

3615


What does the above code synthesize to?

2666


Working of a 2-stage OPAMP?

3242


Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

1543


Explain how logical gates are controlled by Boolean logic?

1242


what is multiplexer?

1228


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3930


Explain how Verilog is different to normal programming language?

1373


what are three regions of operation of MOSFET and how are they used?

1301


Explain what is the depletion region?

1137


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1623


Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3853