Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / dyamanna.siddappa
LVS mean's layout versus schmetic.. compare to layout and
schmetic..
DRC mean's design rule check.. layer to layer between
distence in vlsi layout design
| Is This Answer Correct ? | 8 Yes | 4 No |
Post New Answer View All Answers
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
What is the function of tie-high and tie-low cells?
Explain what is the depletion region?
What are the different design constraints occur in the synthesis phase?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
What is the difference between nmos and pmos technologies?
Explain why is the number of gate inputs to cmos gates usually limited to four?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Write a program to explain the comparator?
What are the steps involved in preventing the metastability?
What does it mean “the channel is pinched off”?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
How can you construct both PMOS and NMOS on a single substrate?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What types of high speed CMOS circuits have you designed?
