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data bus& address bus
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Explain the Working of a 2-stage OPAMP?
How about voltage source?
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Explain various adders and difference between them?
What transistor level design tools are you proficient with? What types of designs were they used on?
Explain the operation of a 6T-SRAM cell?
Explain why is the number of gate inputs to cmos gates usually limited to four?
What is the function of enhancement mode transistor?
What types of CMOS memories have you designed? What were their size? Speed?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
what is multiplexer?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Differences between Array and Booth Multipliers?
Give the cross-sectional diagram of the cmos.
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
