Answer Posted / banibrata

1/2 C V^2.f

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

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Explain the Working of a 2-stage OPAMP?

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What types of CMOS memories have you designed? What were their size? Speed?

3144

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Why does the present vlsi circuits use mosfets instead of bjts?

1298

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What does the above code synthesize to?

2604

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

3003

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2839

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What are the ways to Optimize the Performance of a Difference Amplifier?

2449

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What was your role in the silicon evaluation or product ramp? What tools did you use?

2318

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Are you familiar with the term MESI?

2741

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

1303

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Insights of a 4bit adder/Sub Circuit?

3371

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Basic Stuff related to Perl?

2819

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3867

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

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