Answer Posted / kalaiyarasan

testing: this is done in the production side of IC fabrication
Verification : This is done in the design side of IC

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1257

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What is the main function of metastability in vsdl?

1116

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

2889

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What are the different ways in which antenna violation can be prevented?

1183

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What's the price in 1K quantity?

2886

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1426

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

1253

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What are the changes that are provided to meet design power targets?

1176

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2453

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Mention what are three regions of operation of mosfet and how are they used?

1120

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Design an 8 is to 3 encoder using 4 is to encoder?

1382

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1184

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1239

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1651

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Are you familiar with the term MESI?

2838

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