Differences between functions and Procedures in VHDL?
- 5 Answers
- 52591 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / princehari
VHDL procedures and functions greatly increase the power and
utility of the language for specifying designs. While these
constructs are being used extensively for modeling, most
VHDL synthesis tools limit their synthesis to a single
implementation style such as treating them as a component.
The authors evaluate four techniques for the synthesis of
procedures/functions and discuss their relative merits and
demerits. They examine these implementation styles in the
light of VHDL signals and wait statement semantics. The
results of the various implementation styles are shown on
several examples
| Is This Answer Correct ? | 12 Yes | 26 No |
Post New Answer View All Answers
For CMOS logic, give the various techniques you know to minimize power consumption
What is Body Effect?
Explain the Charge Sharing problem while sampling data from a Bus?
what is verilog?
What is the difference between synchronous and asynchronous reset?
Give the cross-sectional diagram of the cmos.
Explain what is Verilog?
Explain the Various steps in Synthesis?
Are you familiar with the term MESI?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What types of high speed CMOS circuits have you designed?
Explain the working of Insights of a pass gate ?
Explain how binary number can give a signal or convert into a digital signal?
How can you model a SRAM at RTL Level?
Explain what is scr (silicon controlled rectifier)?
