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Differences between functions and Procedures in VHDL?
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Answer Posted / princehari
VHDL procedures and functions greatly increase the power and
utility of the language for specifying designs. While these
constructs are being used extensively for modeling, most
VHDL synthesis tools limit their synthesis to a single
implementation style such as treating them as a component.
The authors evaluate four techniques for the synthesis of
procedures/functions and discuss their relative merits and
demerits. They examine these implementation styles in the
light of VHDL signals and wait statement semantics. The
results of the various implementation styles are shown on
several examples
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