What are set up time & hold time constraints? What do they
signify?
Answer Posted / raghavendra
the setup and hold time constraints are
1.constraint for setup time:the data and clock should be available at the same time
2.constraint for hold time:the data should not change after clock tick.
they signify the correctness of the signal
Is This Answer Correct ? | 3 Yes | 12 No |
Post New Answer View All Answers
Explain the working of Insights of an inverter ?
What transistor level design tools are you proficient with? What types of designs were they used on?
Design an 8 is to 3 encoder using 4 is to encoder?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
What types of CMOS memories have you designed? What were their size? Speed?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
what is the difference between the TTL chips and CMOS chips?
Explain CMOS Inverter transfer characteristics?
Explain how logical gates are controlled by Boolean logic?
Draw the stick diagram of a NOR gate. Optimize it
What is the ideal input and output resistance of a current source?
what is verilog?
Explain sizing of the inverter?
What is the main function of metastability in vsdl?
Write a VLSI program that implements a toll booth controller?