Answer Posted / sarojini
static ram is a volatile memory. so it is easy to model a
sram at rtl level
| Is This Answer Correct ? | 2 Yes | 20 No |
Post New Answer View All Answers
What are the Factors affecting Power Consumption on a chip?
What is the function of tie-high and tie-low cells?
Cross section of a PMOS transistor?
What are the main issues associated with multiprocessor caches and how might you solve them?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What are the different design techniques required to create a layout for digital circuits?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
Explain the working of 4-bit Up/down Counter?
What does the above code synthesize to?
Explain sizing of the inverter?
How binary number can give a signal or convert into a digital signal?
What is the difference between the mealy and moore state machine?
If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.