Advantages and disadvantages of Mealy and Moore?
Answer Posted / akasaramanna
Mr.sudeep r u really knows the answer r not?
endibey badacow ne istamonchina answer isthava?
donganayala?proper ga answer thelistene pumpinchu lekapote
kinda,pina moosukoni kurcho.
| Is This Answer Correct ? | 16 Yes | 31 No |
Post New Answer View All Answers
Explain what is the use of defpararm?
Draw the stick diagram of a NOR gate. Optimize it
What are the steps involved in designing an optimal pad ring?
Explain the working of Insights of an inverter ?
What is the critical path in a SRAM?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
what is the difference between the TTL chips and CMOS chips?
Basic Stuff related to Perl?
What types of high speed CMOS circuits have you designed?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What are the steps involved in preventing the metastability?
What is the ideal input and output resistance of a current source?
Explain what is multiplexer?
What is the function of tie-high and tie-low cells?