Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

what is Latch up?How to avoid Latch up?

Answer Posted / abhishek

Latch up refers to the creation of a low resistance path between power and ground. This is essentially created due to parasitic bipolars getting active.

To minimize chances of latch up:

1. Use of guard rings - they are nothing but a N+ or P+ ring around the device which is suitably biased to power/ground respectively. How they help is that if by chance there are carriers like electrons in the substrate, they are trapped/attracted by the respective wells.

2. Keeping the substrate traps close to the devices This reduces bulk resistance and helps minimize risk of LU

Is This Answer Correct ?    22 Yes 1 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1113


Explain what is multiplexer?

1066


Explain the operation considering a two processor computer system with a cache for each processor.

2835


What products have you designed which have entered high volume production?

2428


What's the price in 1K quantity?

2811


Explain about 6-T XOR gate?

1242


In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

1006


What types of CMOS memories have you designed? What were their size? Speed?

3132


Explain the working of Insights of a pass gate ?

1219


What happens if we use an Inverter instead of the Differential Sense Amplifier?

3299


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1441


What is threshold voltage?

1165


Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

3369


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1191


Mention what are the two types of procedural blocks in Verilog?

1279