Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Are you familiar with the term MESI?

Answer Posted / neto colina

Is a widely used cache coherency and memory coherence
protocol introduced by Intel. Modified Exclusive Shared
Invalid are the protocol States.

M means value has been modified from main memory and the
cache is required to write the data back to main memory,
before permitting any other read of the main memory state.
(ITS DIRTY)

E IS CLEAN: Value Match with main memory

S Cache may be stored in other caches of the machine

I Invalid

Is This Answer Correct ?    12 Yes 6 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Why does the present vlsi circuits use mosfets instead of bjts?

1231


What are the different ways in which antenna violation can be prevented?

1073


For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1229


What is the difference between cmos and bipolar technologies?

1091


What is the difference between nmos and pmos technologies?

1065


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2839


How can you model a SRAM at RTL Level?

5686


What is look up table in vlsi?

942


what is Slack?

1127


For CMOS logic, give the various techniques you know to minimize power consumption

1351


Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1311


Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1401


What is the function of enhancement mode transistor?

1066


Explain sizing of the inverter?

4374


What was your role in the silicon evaluation/product ramp? What tools did you use?

3657