Answer Posted / bhushan

D-Latch is a level sensitive flip-flop.
output changes as long as clock is High(for +ve level
sensitive) or High(for -ve level sensitive)


library ieee;
use ieee.std_logic_1164.all;

entity D_latch is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end D_latch;

architecture arch_D_latch of D_latch is
begin
process(d,clk)
begin
-- +ve level sensitive
if(clk = '1') then
q <= d;
else
q <= q;
end if;
end process;

end arch_D_latch;

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