Interested to Buy Any Domain ? << Click Here >> for more details...
In what cases do you need to double clock a signal before
presenting it to a synchronous state machine?
- 1 Answers
- 5406 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / sudeep
when ur transfering a data b/w two different clock domains,
ex:- The Fsm and ur outside design is working at different
frequencies, to synchronise these signals u do double
clocking to avoid metastability before transferring it into
the FSM.
| Is This Answer Correct ? | 8 Yes | 0 No |
Post New Answer View All Answers
Explain Basic Stuff related to Perl?
What are the different measures that are required to achieve the design for better yield?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Design an 8 is to 3 encoder using 4 is to encoder?
What are the different design constraints occur in the synthesis phase?
What is the critical path in a SRAM?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
Explain the three regions of operation of a mosfet.
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
How about voltage source?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.
Draw a 6-T SRAM Cell and explain the Read and Write operations
Explain the Charge Sharing problem while sampling data from a Bus?
what is Slack?
Give the cross-sectional diagram of the cmos.
