Answer Posted / senthil

I am using the Mr.Suriya code with little modification.

ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= '1';
COUNT:=0;
ELSE
NEWCLK<= '0';
END IF;
END IF;
END PROCESS;
END BEH;

How do you size NMOS and PMOS transistors to increase the threshold voltage?

3086

---

How about voltage source?

2324

---

What are the changes that are provided to meet design power targets?

1175

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1647

---

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1409

---

Are you familiar with the term MESI?

2835

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1172

---

What are the different design techniques required to create a layout for digital circuits?

1093

---

Explain what is the use of defpararm?

1192

---

what is a sequential circuit?

1247

---

What is the ideal input and output resistance of a current source?

3062

---

Differences between Array and Booth Multipliers?

4137

---

6-T XOR gate?

4296

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

2937

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3314

---