Answer Posted / harvir

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;

architecture a of gh_DFF is
begin

process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;

end a;

How binary number can give a signal or convert into a digital signal?

1248

---

Explain the working of 4-bit Up/down Counter?

4441

---

Explain what is Verilog?

1120

---

What is the ideal input and output resistance of a current source?

3017

---

Mention what are the different gates where Boolean logic are applicable?

1139

---

What is the critical path in a SRAM?

3208

---

What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

2453

---

what is a sequential circuit?

1181

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1466

---

Explain what is multiplexer?

1089

---

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1354

---

Explain how Verilog is different to normal programming language?

1290

---

Explain the operation considering a two processor computer system with a cache for each processor.

2862

---

If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1131

---

What happens if we use an Inverter instead of the Differential Sense Amplifier?

3318

---