Answer Posted / garima

1.Dynamic Frequency scaling: use of programmable dividers.
2. Good RTL coding techinques,
1.using clock gating cells during RTL phasing with
intelligent gating enabling logic.
2. using gray coding.
Do not depen entirely on sythesis inserted clock gating
3. Dynamic Voltage scaling.
4. Low power modes: application based most of the cores ex
ARM supports various modes.
5. Power Gating : SRPG.

How to improve these parameters? (Cascode topology, use long channel transistors)

2168

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what is the difference between the TTL chips and CMOS chips?

1105

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Tell me how MOSFET works.

2408

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What types of CMOS memories have you designed? What were their size? Speed?

3128

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1110

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Explain the operation considering a two processor computer system with a cache for each processor.

2833

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What are the steps involved in designing an optimal pad ring?

1153

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Basic Stuff related to Perl?

2801

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1555

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Draw the Layout of an Inverter?

2483

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3769

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Implement a 2 I/P and gate using Tran gates?

3994

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why is the number of gate inputs to CMOS gates usually limited to four?

1324

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Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1088

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Explain what is scr (silicon controlled rectifier)?

1048

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