Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / jelydonut
LVS is when the netlist (normally synthesized verilog) and
the physical layout (gdsii) match connections (ie cells and
wire connections match the physical layout).
DRC is when the physical layout is checked to make sure that
the layout of the part is manufacturable using the process
that the foundry is capable of. (ie if two metal wires are
too close together on the same layer, they may short during
the manufacturing process, affecting yield, just one of many
possible examples on this one)
Some of the other answers are right, but don't explain it well.
| Is This Answer Correct ? | 48 Yes | 6 No |
Post New Answer View All Answers
What's the price in 1K quantity?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Explain what is the use of defpararm?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
What are the different gates where boolean logic are applicable?
Draw the stick diagram of a NOR gate. Optimize it
Explain CMOS Inverter transfer characteristics?
what is Slack?
What is the critical path in a SRAM?
What are the steps required to solve setup and hold violations in vlsi?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Differences between IRSIM and SPICE?
What are the main issues associated with multiprocessor caches and how might you solve them?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What is the difference between the mealy and moore state machine?
