Answer Posted / gogulnath
field programmable gate array,it is the tool which is
readily available in market to simulate the language
| Is This Answer Correct ? | 0 Yes | 40 No |
Post New Answer View All Answers
What types of CMOS memories have you designed? What were their size? Speed?
What happens if we delay the enabling of Clock signal?
Explain what is the depletion region?
Explain the working of Insights of a pass gate ?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What does the above code synthesize to?
In Verilog code what does “timescale 1 ns/ 1 ps” signifies?
Explain what is scr (silicon controlled rectifier)?
What are the various regions of operation of mosfet? How are those regions used?
What is the difference between nmos and pmos technologies?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
What is the difference between the mealy and moore state machine?
What transistor level design tools are you proficient with? What types of designs were they used on?
Explain about 6-T XOR gate?