What are set up time & hold time constraints? What do they
signify?
Answer Posted / guest
Setup time: Time before the active clock edge of the
flipflop, the input should be stable. If the signal changes
state during this interval, the output of that flipflop
cann't be predictable (called metastable).
Hold Time: The after the active clock edge of the flipflop,
the input should be stable. If the signal changes during
this interval, the output of that flipflop cann't be
predictable (called metastable).
| Is This Answer Correct ? | 51 Yes | 4 No |
Post New Answer View All Answers
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
Explain what is Verilog?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
Implement a 2 I/P and gate using Tran gates?
Design an 8 is to 3 encoder using 4 is to encoder?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
Explain how logical gates are controlled by Boolean logic?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Explain Basic Stuff related to Perl?
What does the above code synthesize to?
Explain about 6-T XOR gate?
Working of a 2-stage OPAMP?
What are the steps involved in preventing the metastability?