What are set up time & hold time constraints? What do they
signify?
Answer Posted / guest
Setup time: Time before the active clock edge of the
flipflop, the input should be stable. If the signal changes
state during this interval, the output of that flipflop
cann't be predictable (called metastable).
Hold Time: The after the active clock edge of the flipflop,
the input should be stable. If the signal changes during
this interval, the output of that flipflop cann't be
predictable (called metastable).
| Is This Answer Correct ? | 51 Yes | 4 No |
Post New Answer View All Answers
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Mention what are the two types of procedural blocks in Verilog?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
What types of high speed CMOS circuits have you designed?
What transistor level design tools are you proficient with? What types of designs were they used on?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Explain the working of Insights of an inverter ?
What is the main function of metastability in vsdl?
Insights of a 4bit adder/Sub Circuit?
Write a program to explain the comparator?
Explain depletion region.
What are the different design constraints occur in the synthesis phase?
What products have you designed which have entered high volume production?