In what way interrupts are classified in 8085?

1222

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what are the various flags used in 8085?

1328

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what is program counter?

1163

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Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1158

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1408

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1240

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

1252

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Draw the stick diagram of a NOR gate. Optimize it

1331

---

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1253

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1184

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1172

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

1201

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Draw a 6-T SRAM Cell and explain the Read and Write operations

1336

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1713

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1614

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