Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / ketan
yes the above answer is true and this condition arises as the time period of the flip flop clock is less than the time period of input clock. so as long as the input clock stays high output of flip flop will keep changing.
this can be avoided by using master slave flip flop in which two jk flip flop are connected but each is provided complementary clock pulse i.e. if master has high clock pulse than slave will be having low clock pulse. so till the clock pulse of master flip flop is high then slave clock pulse will be low, and it's output will not change and when slave has high clock pulse then output will change and in that case master will be inactive as it's clock pulse will be low.
| Is This Answer Correct ? | 6 Yes | 0 No |
Post New Answer View All Answers
What is inductor?
What is meant by cyclo-converter?
how can I pass ccna in first try in one month
Tell me, when a sample of germanium and silicon having same impurity density are kept at room temperature then resistivity of silicon will be higher than that of germanium, why?
What is the correct way of weather proofing?
What are the various logic gates?
What is a combinational circuit?
What is the output power of a BTS, in dbm &watts if trx=2+2+2... if trx=4+4+4..
What is meant a series inverter?
Why does sidebands vl come in case of analog modulation?
Explain why open-loop op-amp configurations are not used in linear applications?
What principle does a q-meter operate?
What is Cycling Frequency Hopping?
What is a p-n junction diode? State and explain some of its applications.
i am b.sec with PCM now what can i do for higher education
