what is race around condition
Answer Posted / baisakhi khasnabis
we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
| Is This Answer Correct ? | 308 Yes | 16 No |
Post New Answer View All Answers
Define hold time?
How the earting for portable DG set is done?
why should you consider youself fit to be hired by jspl
In automation process timer based automation is best or not? any other possible methods are available
hai i am balaji now i applied for the post of section engineer in rrb chennai............ if any body know the question peper and pattern of written exam please send to me
What is an fpga?
Explain the structure of entire GSM.
Can you please send me the previous 10 years solved question papers of GATE ?
What are potential transformers?
What is space charge width?
Tell me why the shape of op-amp is triangular not other shape?
why is the diffusion technique of formation of resistor most widely used?
what is the difference between DVB-S& DVB-S2
What is the internal structure of op-amp and explain each block in brief?
Explain the purpose of the package around a microprocessor silicon die?