Answer Posted / abc

Answer 2 is wrong. latch can have a clock. Answer 1 is correct.
elaborating on it: difference is that for a latch the output
can follow input(like a buffer) if latch is in "pass" state,
else if the clock input is such that the its in "latch"
state then output is preserved. Whereas, flip-flop output
only changes at the clock edge(rising or falling depending
upon type of flop)

What types of high speed CMOS circuits have you designed?

2577

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

1279

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6-T XOR gate?

4251

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What does the above code synthesize to?

2606

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What are the steps involved in designing an optimal pad ring?

1172

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Draw the Layout of an Inverter?

2507

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Write a program to explain the comparator?

1158

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What are the different design constraints occur in the synthesis phase?

1101

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If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1124

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1221

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1204

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Give various factors on which threshold voltage depends.

1306

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What's the price in 1K quantity?

2826

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

3314

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Explain Cross section of a PMOS transistor?

1234

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