Interested to Buy Any Domain ? << Click Here >> for more details...
Answer Posted / madhu
When a clock is triggered, if it reaches first to
destination and next to source then we have a loss of
data,or if it reaches first to source and later to
destination we have a wrong result .this is called Clock
skew,so it is necessary to a clock to reach simultaneously
to source and destination.
| Is This Answer Correct ? | 22 Yes | 29 No |
Post New Answer View All Answers
For CMOS logic, give the various techniques you know to minimize power consumption
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain what is the depletion region?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What are the Factors affecting Power Consumption on a chip?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Are you familiar with the term snooping?
If not into production, how far did you follow the design and why did not you see it into production?
Explain why present VLSI circuits use MOSFETs instead of BJTs?
Draw the stick diagram of a NOR gate. Optimize it
Differences between IRSIM and SPICE?
Explain sizing of the inverter?
