Answer Posted / rahul singhal

-----By RAHUL SINGHAL----
----This is the code of a FSM that implements a toll booth -
----controller


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of
specific package---

ENTITY tollbooth2 IS
PORT (Clock,car_s,RE : IN STD_LOGIC;
coin_s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
r_light,g_light,alarm : OUT STD_LOGIC);
END tollbooth2;

ARCHITECTURE Behav OF tollbooth2 IS
TYPE state_type IS
(NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE
D);
------GOTZERO = PAID $0.00---------
------GOTFIV = PAID $0.05----------
------GOTTEN = PAID $0.10----------
------GOTFIF = PAID $0.15----------
------GOTTWEN = PAID $0.20---------
SIGNAL present_state,next_state : state_type;

BEGIN
-----Next state is identified using present state,car &
coin sensors------
PROCESS(present_state,car_s,coin_s)
BEGIN

CASE present_state IS
WHEN NO_CAR =>
IF (car_s = '1') THEN
next_state <= GOTZERO;
ELSE
next_state <= NO_CAR;
END IF;

WHEN GOTZERO =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTZERO;
ELSIF (coin_s = "01") THEN
next_state <= GOTFIV;
ELSIF (coin_s ="10") THEN
next_state <= GOTTEN;
END IF;

WHEN GOTFIV=>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTFIV;

ELSIF (coin_s = "01") THEN
next_state <= GOTTEN;
ELSIF (coin_s <= "10") THEN
next_state <= GOTFIV;
END IF;

WHEN GOTTEN =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s ="00") THEN
next_state <= GOTTEN;

ELSIF (coin_s="01") THEN
next_state <= GOTFIV;
ELSIF (coin_s="10") THEN
next_state <= GOTTWEN;
END IF;

WHEN GOTFIF =>
IF (car_s ='0') THEN
next_state <= CHEATED;
ELSIF (coin_s = "00") THEN
next_state <= GOTFIF;

ELSIF (coin_s ="01") THEN
next_state <= GOTTWEN;
ELSIF (coin_s = "10") THEN
next_state <= GOTTWEN;
END IF;

WHEN GOTTWEN =>
next_state <= CAR_PAID;

WHEN CAR_PAID =>
IF (car_s = '0') THEN
next_state <= NO_CAR;
ELSE
next_state<= CAR_PAID;
END IF;

WHEN CHEATED =>
IF (car_s = '1') THEN
next_state <= GOTZERO;
ELSE
next_state <= CHEATED;
END IF;

END CASE;
END PROCESS;-----End of Process 1
-------PROCESS 2 for STATE REGISTER CLOCKING--------
PROCESS(Clock,RE)
BEGIN
IF RE = '1' THEN
present_state <= GOTZERO;
----When the clock changes from low to high,the state of
the system
----stored in next_state becomes the present state-----
ELSIF Clock'EVENT AND Clock ='1' THEN
present_state <= next_state;
END IF;
END PROCESS;-----End of Process 2-------
---------------------------------------------------------
-----Conditional signal assignment statements----------
r_light <= '0' WHEN present_state = CAR_PAID ELSE '1';
g_light <= '1' WHEN present_state = CAR_PAID ELSE '0';
alarm <= '1' WHEN present_state = CHEATED ELSE '0';
END Behav;

On a scale of one to ten, rate me as an interviewer now 26 which stack is used in 8086?

1032

---

what is the difference between timer and counter of microcontroller?

1290

---

What are the advantages of memory segmentation in 8086

1212

---

Mention the types of interrupts that 8085 supports?

1061

---

Explain the purpose of the status register?

1096

---

I have code and test bench however it is not working porperly. Need help to get it working. module fsm(clock,reset,coin,vend,state,change); \\these are the inputs and the outputs. input clock; input reset; input [2:0]coin; output vend; output [2:0]state; output [2:0]change; \\i need to define the registers as change,coin and vend reg vend; reg [2:0]change; wire [2:0]coin; \\my coins are declared as parameters to make reading better. parameter [2:0]NICKEL=3’b001; parameter [2:0]DIME=3’b010; parameter [2:0]NICKEL_DIME=3’b011; parameter [2:0]DIME_DIME=3’b100; parameter [2:0]QUARTER=3’b101; \\MY STATES ARE ALSO PARAMETERS . I DONT WANT TO MAKE YOU READ \\IN MACHINE LANGUAGE parameter [2:0]IDLE=3’b000; parameter [2:0]FIVE=3’b001; parameter [2:0]TEN=3’b010; parameter [2:0]FIFTEEN=3’b011; parameter [2:0]TWENTY=3’b100; parameter [2:0]TWENTYFIVE=3’b101; \\AS ALWAYS THE STATES ARE DEFINED AS REG reg [2:0]state,next_state; \\MY MACHINE WORKS ON STATE AND COIN always @(state or coin) begin next_state=0; \\VERYFIRST NEXT STATE IS GIVEN ZERO case(state) IDLE: case(coin) \\THIS IS THE IDLE STATE NICKEL: next_state=FIVE; DIME: next_state=TEN; QUARTER: next_state=TWENTYFIVE; default: next_state=IDLE; endcase FIVE: case(coin) \\THIS IS THE SECOND STATE NICKEL: next_state=TEN; DIME: next_state=FIFTEEN; QUARTER: next_state=TWENTYFIVE; //change=NICKEL default: next_state=FIVE; endcase TEN: case(coin) \\THIS IS THE THIRD STATE NICKEL: next_state=FIFTEEN; DIME: next_state=TWENTY; QUARTER: next_state=TWENTYFIVE; //change=DIME default: next_state=TEN; endcase FIFTEEN: case(coin) \\THIS IS THE FOURTH STATE NICKEL: next_state=TWENTY; DIME: next_state=TWENTYFIVE; QUARTER: next_state=TWENTYFIVE; //change==NICKEL_DIME default: next_state=FIFTEEN; endcase TWENTY: case(coin) \\THIS IS THE FIFTH STATE NICKEL: next_state=TWENTYFIVE; DIME: next_state=TWENTYFIVE; //change=NICKEL QUARTER: next_state=TWENTYFIVE; //change==DIME_DIME default: next_state=TWENTY; endcase TWENTYFIVE: next_state=IDLE; \\THE NEXT STATE HERE IS THE RESET default : next_state=IDLE; endcase end always @(clock) begin \\WHENEVER I GIVE A RESET I HAVE TO MAKE THE STATE TO IDLE AND VEND TO 1 if(reset) begin state <= IDLE; vend <= 1’b0; // change <= 3’b000; end \\THE CHANGE ALSO HAS TO BECOME NONE else state <= next_state; case (state) \\HERE WE DECIDE THE NEXT STATE \\ALL THE STATES ARE DEFINED HERE AND THE OUTPUT IS ALSO GIVEN IDLE: begin vend <= 1’b0; change <=3’d0; end FIVE: begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL; else change <=3’d0; TEN: begin vend <= 1’b0; if (coin==QUARTER) change <=DIME; else change <= 3’d0; FIFTEEN : begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL_DIME; else change TWENTY : begin vend <= 1’b0; if (coin==DIME) change <=NICKEL; else if (coin==QUARTER) TWENTYFIVE : begin vend <= 1’b1; change <=3’d0; end default: state <= IDLE; endcase end endmodule module test; \\THE INPUT IN THE FSM MODULE ARE REG HERE reg clock,reset; reg [2:0]coin; \\THE OUTPUT IN THE FSM MODULE ARE WIRES HERE wire vend; wire [2:0]state; wire [2:0]change; \\THE PARAMETERS AGAIN FOR THE COIN AND STATE parameter [2:0]IDLE=3’b000; parameter [2:0]FIVE=3’b001; parameter [2:0]TEN=3’b010; parameter [2:0]FIFTEEN=3’b011; parameter [2:0]TWENTY=3’b100; parameter [2:0]TWENTYFIVE=3’b101; parameter [2:0]NICKEL=3’b001; parameter [2:0]DIME=3’b010; parameter [2:0]NICKEL_DIME=3’b011; parameter [2:0]DIME_DIME=3’b100; parameter [2:0]QUARTER=3’b101; \\I MONITOR THE TIME,DRINK,RESET,CLOCK,STATE AND CHANGE FOR CHANGES. initial begin $display("Time\tcoin\tdrink\treset\tclock\tstate\tchange"); $monitor("%g\t%b\t%b\t%b\t%b\t%d\t% d",$time,coin,vend,reset,clock,state,change); \\NEW FEATURE: MY MACHINE HAS THE FACILITY TO DUMP VARIABLES SO THAT \\ I CAN VIEW THEM USING A VCD VIEWER. $dumpvars; $dumpfile("file.vcd"); // Dump output file. \\THIS IS WHERE THE COINS ARE ADDED. clock=0; reset=1; \\FIRST LETS RESET THE MACHINE #2 reset=0; coin=NICKEL; \\CHECK FOR STATE 1 #2 reset=1; coin=2’b00; #2 reset=0; coin=DIME; \\RESET AGAIN AND CHECK FOR STATE 2 #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 reset=1; coin=2’b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 AND SO ON coin=NICKEL; #2 coin=DIME; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=DIME; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 reset=0; coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2’b00; #2 $finish; end \\THE CLOCK NEEDS TO TICK EVERY 2 TIME UNIT always #1 clock=~clock; //always @(state) // coin=!coin; initial begin if (reset) coin=2’b00; end \\THIS IS WHERE I INSTANTIATE THE MACHINE fsm inst1(clock,reset,coin,vend,state,change); endmodule

3926

---

What are the main differences between the 8085 and 8086 microprocessor?

1122

---

Which 2 ports combine to form the 16 bit address for external memory access?

1295

---

Name the pin in 8086 microprocessor that is used for selecting mode of operation?

1181

---

What is the the total addressable memory size in a 8085 microprocessor?

1086

---

Why memory width is not 16-bit? In stead of having 8-bit (same as 8085)?

1160

---

Explain the two types of software?

1081

---

Define what the sop does with the help of an example.

1026

---

What is the significance of the control unit in the 8085?

1056

---

What is the bit size of Itanium processor of Intel?

1142

---