Answer Posted / harshgandhi126
TRI state inverter has 3 states i.e. HIGH,LOW and HIGH
IMPEDENCE (Z). It has 2 inputs. One is normal input and
another is ENABLE. If ENABLE is LOW then inverter is in
HIGH IMPEDENCE state, otherwise it acts as a normal
inverter (if ENABLE=1).
ENABLE I/P O/P
0 X Z (HIGH IMPEDENCE)
1 0 1
1 1 0
Is This Answer Correct ? | 3 Yes | 0 No |
Post New Answer View All Answers
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
How binary number can give a signal or convert into a digital signal?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
What does it mean “the channel is pinched off”?
What is the difference between synchronous and asynchronous reset?
In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?
What's the price in 1K quantity?
How can you model a SRAM at RTL Level?
Give various factors on which threshold voltage depends.
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Design an 8 is to 3 encoder using 4 is to encoder?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain the Working of a 2-stage OPAMP?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
What are the different design constraints occur in the synthesis phase?