Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

What is Cross Talk?

Answer Posted / jay patel

cross talk is basically a coupling of portion of energy of
one part of system into another one.

it occurs due to electrically coupling or magnetically coupling,

as two traces in circuit are separated there is a mutual
capacitance exist depend on spacing and potential differance
and so coupled voltage into another

simillarly when current flow in trace magnetic field induced
and get coupled into another due to mutual inductance.
magnitude of it depend on differance in current in both one.

cross talk is major linmiting factor in circuit design

Is This Answer Correct ?    1 Yes 0 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1543


You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

1505


what is the difference between the TTL chips and CMOS chips?

1066


What is the difference between cmos and bipolar technologies?

1087


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

1142


Explain Cross section of an NMOS transistor?

980


You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2627


What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

3210


What is the difference between nmos and pmos technologies?

1060


What are the different ways in which antenna violation can be prevented?

1070


Explain the operation considering a two processor computer system with a cache for each processor.

2813


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3822


Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

1249


Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1087


What is Body Effect?

2465