What happens if we delay the enabling of Clock signal?
- 4 Answers
- 5780 Views
- I also Faced
- E-Mail Answers
Answer Posted / asan ibrahim
skew will apear
| Is This Answer Correct ? | 0 Yes | 0 No |
Post New Answer View All Answers
What are the different classification of the timing control?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain depletion region.
Write a program to explain the comparator?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What are the Advantages and disadvantages of Mealy and Moore?
What is the difference between nmos and pmos technologies?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Explain how MOSFET works?
what is verilog?
Draw the Layout of an Inverter?
Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
How can you construct both PMOS and NMOS on a single substrate?
Explain how logical gates are controlled by Boolean logic?
Explain the operation considering a two processor computer system with a cache for each processor.
