What is D-FF?
What is the basic difference between Latches and Flip flops?
What is a multiplexer?
How can you convert an SR Flip-flop to a JK Flip-flop?
How can you convert an JK Flip-flop to a D Flip-flop?
What is Race-around problem? How can you rectify it?
Which semiconductor device is used as a voltage regulator and why?
Explain an ideal voltage source?
Explain zener breakdown and avalanche breakdown?
What are the different types of filters?
What is the need of filtering ideal response of filters and actual response of filters?
What is sampling theorem?
What is impulse response?
Explain the advantages and disadvantages of FIR filters compared to IIR counterparts.
What is CMRR?
Explain half-duplex and full-duplex communication?
Which range of signals is used for terrestrial transmission?
Why is there need for modulation?
Which type of modulation is used in TV transmission?
Why we use vestigial side band (VSB-C3F) transmission for picture?
When transmitting digital signals is it necessary to transmit some harmonics in addition to fundamental frequency?
For asynchronous transmission, is it necessary to supply some synchronizing pulses additionally or to supply or to supply start and stop bit?
BPFSK is more efficient than BFSK in presence of noise. Why?
What is meant by pre-emphasis and de-emphasis?
Explain 3 dB cutoff frequency? Why is it 3 dB, not 1 dB?
Explain ASCII, EBCDIC?
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Answer Posted / dileep goyal
1.The edge-triggered D flip-flop is easily derived from its
RS counterpart. The only requirement is to replace the R
input with an inverted version of the S input, which
thereby becomes D. This is only needed in the master latch
section; the slave remains unchanged.
One essential point about the D flip-flop is that when the
clock input falls to logic 0 and the outputs can change
state, the Q output always takes on the state of the D
input at the moment of the clock edge. This was not true of
the RS and JK flip-flops. The RS master section would
repeatedly change states to match the input signals while
the clock line is logic 1, and the Q output would reflect
whichever input most recently received an active signal.
The JK master section would receive and hold an input to
tell it to change state, and never change that state until
the next cycle of the clock. This behavior is not possible
with a D flip-flop.
2.Latchs: They are sensitive to the duration of pulse and
can transfer data until they are switched on. They hold the
last logic at the output if we put it off(bring the strobe
pin to low). They are used as temporary buffers.
FF: They are sensitive to signal change(low to high or
high to low) and not the level. Hence they transfer data
only at that instant and it cannot be changed until next
signal change. Due to this they are used as registers.
3.multiplexer is a device whan we give the one and more
input tnan it combine this and give only one output
4.By connecting J&K input terminal with a not gate. now
input
at j terminal.
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