What happens if we delay the enabling of Clock signal?
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What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What is Body Effect?
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
Draw a CMOS Inverter. Explain its transfer characteristics
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
Explain the three regions of operation of a mosfet.
What are the steps involved in designing an optimal pad ring?
What are the main issues associated with multiprocessor caches and how might you solve them?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What transistor level design tools are you proficient with? What types of designs were they used on?
What does the above code synthesize to?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
Implement a 2 I/P and gate using Tran gates?
How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
