Answer Posted / gourab varma

#include<stdio.h>
#include<conio.h>
void main()
{
int a,b;
clrscr();
printf("enter value of a and b");
scanf("%d%d", &a,&b);
a=a+b;
b=a-b;
a=a-b;
printf("the value of a=%d\n the value of b is=%d", a, b);
getch();
}

Can i please VHDL code for D-Latch with clear input ?? (HINT: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs and Outputs: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

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