Answer Posted / anuprita
In circuit designs, clock skew is a phenomenon in
synchronous circuits in which the clock signal arrives at
different components at different times. This can be caused
by many different things, such as wire-interconnect length,
temperature variations, variation in intermediate devices,
capacitive coupling, material imperfections, and
differences in input capacitance on the clock inputs of
devices using the clock.
Is This Answer Correct ? | 27 Yes | 0 No |
Post New Answer View All Answers
Mention what are the different gates where Boolean logic are applicable?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What is the critical path in a SRAM?
Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
what is multiplexer?
Explain what is Verilog?
If not into production, how far did you follow the design and why did not you see it into production?
what is the difference between the TTL chips and CMOS chips?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Implement a function with both ratioes and domino logic and merits and demerits of each logic?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
Explain what is the use of defpararm?
Design an 8 is to 3 encoder using 4 is to encoder?
What is the function of enhancement mode transistor?
What does it mean “the channel is pinched off”?