Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

Explain Custom Design Flow?

Answer Posted / amar

Custom IC design requires if the circuit has to be designed to
meet the maximum possible performance requirements.

In this case the transistor parameters are tuned to meet the
required overall circuit performance

This kind of design methodology is specifically used
in analog design , mixed signals design and RF design

Is This Answer Correct ?    0 Yes 3 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

1155


What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

1206


Explain what is the use of defpararm?

1098


What products have you designed which have entered high volume production?

2392


How to improve these parameters? (Cascode topology, use long channel transistors)

2131


what is a sequential circuit?

1088


Explain how logical gates are controlled by Boolean logic?

1125


Explain how MOSFET works?

3194


If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1063


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3821


Explain what is the depletion region?

1029


what is multiplexer?

1098


Insights of a 4bit adder/Sub Circuit?

3293


What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

1244


Draw the stick diagram of a NOR gate. Optimize it

1225