Answer Posted / k.n.n.sarma

LATCH-LEVEL SENSITIVE
IT CONSISTS OF BOTH ENABLE AND CLOCK



FLIP FLOP-EDGE TRIGGERED
IT CONSISTS OF ONLY CLOCK AND NO ENABLE IS PRESENT FOR FLIP
FLOP.

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2624

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what is multiplexer?

1098

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What are the different design techniques required to create a layout for digital circuits?

994

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

1148

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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

1127

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

1247

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What are the different classification of the timing control?

1050

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Explain the Various steps in Synthesis?

3224

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3821

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Design an 8 is to 3 encoder using 4 is to encoder?

1290

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Give the cross-sectional diagram of the cmos.

942

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How binary number can give a signal or convert into a digital signal?

1136

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What are the different measures that are required to achieve the design for better yield?

1164

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

1057

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

1206

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