Answer Posted / sada

latch is level sensitive but not flip flop

What are the different design constraints occur in the synthesis phase?

1062

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What are the different measures that are required to achieve the design for better yield?

1161

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what is Slack?

1123

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In vlsi chip 1000s of transistors are dropped, specifically categorized. Which method is used to achieve this & how it is done practically?

971

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What happens if we delay the enabling of Clock signal?

2299

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Explain what is slack?

1014

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

3728

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why is the number of gate inputs to CMOS gates usually limited to four?

1277

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What types of high speed CMOS circuits have you designed?

2506

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3820

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1148

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What does the above code synthesize to?

2519

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How binary number can give a signal or convert into a digital signal?

1135

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What types of CMOS memories have you designed? What were their size? Speed?

4604

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Mention what are the different gates where Boolean logic are applicable?

1057

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