Answer Posted / sada

latch is level sensitive but not flip flop

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

1190

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

1193

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Explain Basic Stuff related to Perl?

1023

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Mention what are the two types of procedural blocks in Verilog?

1273

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Explain Cross section of an NMOS transistor?

1016

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what is the difference between the TTL chips and CMOS chips?

1105

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Differences between IRSIM and SPICE?

5420

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Insights of a 4bit adder/Sub Circuit?

3343

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How binary number can give a signal or convert into a digital signal?

1211

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

2482

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

1579

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Draw the SRAM Write Circuitry

1164

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What are the various regions of operation of mosfet? How are those regions used?

1119

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

2378

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Explain the working of Insights of a pass gate ?

1210

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