Answer Posted / divakar mani tripathi

In a J.K(jack kilby) flip flop when we put a condition I.e j=k=1
Then the output of the f.f starts giving response and changes its
value from 0 to 1 and viceversa by the factor of propagation delay
which is equal to the time take by the input to propagate through two NAND gates .As we known the propagation delay of a NAND state is much smaller compared to a general clock pulse time period .So during single clock period output changes many times uncertainly termed as RACING and the signal o/p is termed as racing signal.

To avoid this there are two ways..
1.To make clock period smaller than propagation delay which is much difficult to implement.
2.By having a MASTER SLAVEconfiguration(I.e by having two jk f.f having the inversion of master clock to the slave clock )by which when the master clock is high then the save clock is low by their alternative working we get the response in a whole period and then changes only in other period this is called TOGGLING which can be used furthur....THANKS

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