how 2 design a mod 6 synchronous counter using jk flip flop?
- 3 Answers
- 23127 Views
- I also Faced
- E-Mail Answers
Answer Posted / aniket
binary for 6 is 110..we will need 3 MS JK FF i.e. using ic
7476....we need to design a truth table for that...
till state 0 to 5(6 states) put your o/p as 1...ie.e those
are valid states and for the remaining ones those are the
invalid states....then draw k-map and design the
combinational logic....put all ur preset and J0 K0..i/ps of
FF to logic 1 and accordingly clock the FF
and put the o/p of the combinaional logic to the clear of
thr ff......in order to clear the states after 5th.....
hope this was usefull....
| Is This Answer Correct ? | 33 Yes | 8 No |
Post New Answer View All Answers
how a definite tx line can acts as indefinite tx line
howw can we transmit the call of gsm?
Explain digital circuits?
Explain why the input impedance of op-amp is so high?
What principle does a q-meter operate?
can we calculate the voltage level for microwave energy which is using for our mobile communication?
What is meant by impedance diagram?
#include int main() { char c='1'; int j=atoi(c); }
What are level triggered flip flop?
Which of the transistor currents is always the largest? Which is always the smallest? Which two currents are relatively close in magnitude?
What are the disadvantages of pwm control?
Explain the differences between microprocessor and micro controller?
charge at rest result in e.f and charge in motion result in m.f then how can an accelerated charge give rise to emf wave? then there should be no e.f due to acc charge as it rise from charge at rest?
plz give the question about interview to the post JR.Executive (ATC)
What is the wave equation for the sound waves encountered in smart cell phones, specifically android?
