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What is Race-around problem? How can you rectify it?
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Answer Posted / suresh ambati
when J and K are 1 output is complementing. Assume clock
period is 10ns and path delay is 2ns .That means for every
2ns output is changing when clock is active.In j k latch
clock pulse is high for 5ns in this case.Assume present
state Qn = 0 .for the first 2ns next state Qn+1 = 1 , and
for the next 2ns i.e at 4ns next state Qn+1 = 0 for the same
clock.Output is not stable for single clock period.This is
race around condition.This is eliminated by master slave jk
flip flop.
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