what is race around condition
Answer Posted / abhinandan kumar
we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
so this can be avoided by using only edgetriggerd ff
rahter than using level triggerd.
| Is This Answer Correct ? | 28 Yes | 9 No |
Post New Answer View All Answers
need previous placement test papers of infosys and soctronics
What is meant by unidirectional or half-wave ac voltage controller?
box1-2 box2-12 box3-350 using multiplication and division only bring 74 in box 3 in 3steps
Power mosfet is a voltage controlled device. Why?
How can I understand electronic/electrical panel wiring & drawing?
i want exam information bhel, nal, hal, bel you have any idea or any question papers or placement papers please send soon
if a PTC having operating voltage 230V is not available then Can we short the circuit where PTC inserted or anybody having other solution. if yes, please reply hurry.
Op-amp is used mostly as an integrator than a differentiator. Explain why?
hai i am balaji now i applied for the post of section engineer in rrb chennai............ if any body know the question peper and pattern of written exam please send to me
what is signal integrity and what is the use ?
What is a combinational circuit?
Define awgn.
WHEN SUB. A IS HPLMN AND B SUB. IS ROAMING FROM ANOTHER PLMN CAN ANY ONE TELL ME THE CALL FLOW FOR THIS?
Explain the difference between emulator and simulator?
How Passive cards like Back planes to be tested throughly?