Answer Posted / mann

its disadvantage is that if we keep the cmos switched on
for lomng time, it gets damaged more easily than any other.

can any one help me out by posting something related to rvnl interview for site engineer electronics (S & T).? what is the procedure? what type of question they generally ask? how long the interview goes for one candidate? and any tips ??

1978

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how the silicon knows 0's and 1's...

1917

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What is vom?

1333

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hi i am electronics & telecomm engg & appling for apprentiship written test and interview. pls forward me the syllabus & old question papers.I will be very much thankful to you. pis inform to 88.avinashkalegmail.com

1932

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10 bit A/D converters,the quantization error in % is??

4843

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Explain why an ammeter should be of very low resistance?

1083

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Explain how does a signal differ from a wave?

1060

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when will give ta

2017

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What is fbus protocol?

1064

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What are edge triggered flip flop and level triggered flip flop? How do they differ from one another?

1104

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What is meant by CDOT in relation to the Communication in BSNL? Explain the term CDOT.

2616

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how to use single phase supply for 3 phase instrumentation

2267

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Explain how to manufacture the cmos inverter?

1086

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does RS-485 cables come with armour?

2068

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What is the distance from an RF Transmitter that output power is determined?

2312

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