Interested to Buy Any Domain ? << Click Here >> for more details...
The reason why the sending end and receiving end voltage
sare almost equal when capacitive load is added.
- 4 Answers
- 11262 Views
- I also Faced
- E-Mail Answers
Answer Posted / guest
Hello. For our university experiment (power transmission
lines) , at first,
we only had a resistive load, and it was shown that
the sending end voltage is bigger than receiving end
voltage. However, when the capacitive load was added in
parallel to the resistive load, it was shown that the
sending end voltage was approximately equal to the
receiving end voltage. Why is it so?
Thank you and have a great day.
| Is This Answer Correct ? | 2 Yes | 0 No |
Post New Answer View All Answers
What is BusBar integrity test and how it is conducted?
what are the main applications of transistor in non-linear region?
what you have to see after one week or month from the day of installation of transformer ?
all the technical question with answers pleas send your email id ramar_eee@yahoo.com
What is minimum permicible value of leackage current for LT Panle when applying voltage up to 3 KV for 5 Minuits?
what is the chiller and working principal
How does the phase sequence controller works, how it identifies the phases? confirm working principle
hi this is hema can anyone mail me previous years questions for the APPSC-A.E.E (in electrical stream.) ......thank u.
How will calculate losses in an multi core Aluminium LT cable of different sizes & upto what length we can use a LT Cable ?
What is gross error?
How is operate breaker failure scheme in substation
hwat type of motor is used in thermal gas turbine hydro nuclear power plants and why
How to calculate the phase to phase clearness of HT /// LT bus bar?????
What are the advantages of autotransformer?
what is a vector protection in transformer
