One type of memory currently of interest utilizes magnetic
tunneling junctions in the memory cells. A magnetic
tunneling junction typically includes two ferromagnetic
layers separated by a thin insulating layer. The insulating
layer is thin enough to allow charge carriers to tunnel
between the ferromagnetic layers. One ferromagnetic layer
has its magnetization fixed, or pinned, in place. This is
typically accomplished using an antiferromagnetic layer. The
other ferromagnetic layer has a magnetization that can
rotate in response to an applied magnetic field. The
resistance of the magnetic tunneling junction depends upon
the orientation of the magnetic tunneling junctions. Thus in
order to store data in the magnetic tunneling junction, a
magnetic field is applied to rotate the magnetization of one
of the layers. Typically, the magnetization of one
ferromagnetic layer will be rotated to be parallel or
anti-parallel to the magnetization of the other
ferromagnetic layer. The magnetic tunneling junction will
thus be in either a low resistance (magnetizations parallel)
or a high resistance (magnetizations antiparallel) state to
represent a “0” or a “1”, respectively. A signal
corresponding to the resistance is developed in order to
indicate the value of the data stored.


Improvements in microprocessor designs has lead to
microprocessors with a high operating frequency. Current
microprocessor designs exceed operating frequencies of 100
megahertz ("MHz"). However, the increase in operating
frequency has not lead to excepted performance gains. One of
the main components affecting performance gains is created
by the microprocessor execution units idling during delays
in external memory access. The delays in external memory
access are caused by the inductive losses associated with
off chip transmissions. The delays in external memory access
are also caused by the conventional design characteristics
of static random access memory ("SRAM") cells and dynamic
random access memory ("DRAM") cells.

To counteract the performance losses associated with
external memory access conventional microprocessor designs
developed cache systems. The cache systems store copies of
external data internal to the microprocessor, thus avoiding
the performance loss created by accessing external memory.
One disadvantage of the conventional cache system is that
the cache systems requires consistent updating to ensure
data coherency. Because the updating process requires access
to external memory intermittent delay cycles still exists
within the microprocessor.

FIG. 1 illustrates a prior art cache system. Processor 100
is coupled to external memory 120 via XBUS 130. Using XBUS
130, processor 100 is able to store and retrieve data from
external memory 120. Processor 100 also includes cache 110.
Cache 110 is used to store copies of data included in
external memory 120, thus reducing processor 100 access to
external memory 120. By reducing the frequency of access to
external memory 120, processor 100 reduces idle cycles, thus
increasing the throughput of executions within processor 100.