hello world program

Matrix

program for interlocking train movement

write a program to list all the duplicate strings present 
in the given array.

Animation of running train.

animation of train

jigs and fixtures

Dynamic CMOS ckts and high speed multipliers using
BOOTh/Mod-Booth algorithm.

yes

yes

vhdl is very high speep integrated chips hardware 
descripted language and verilog is to verify logic

yes

'=' in  c is the assignment opperator.whereas '==' is the 
logical equality operator.

= is the assignment operator while == is equality operator

= is assignment operator & == is equality operator in C
= operator is used to assign a value to the variable
== operator is used to compare two variables.

I NEED MORE....

= is used for assigning the value to a variable
for example
int a=10;
if a=5
printf("%d",a);
else
printf("%d",a);

output:5
in this program a value is assigned to 5 and 5 is printed.

whereas
== is used to check the value of the variable
for example
int a=10;
if a==5
printf("%d",++a);
else
printf("%d",a);

output:10

in this value of a is checked with 10 .If it is equal if 
stmt is true and a is incrementd and printed.
If it is not equal a value is printed.

To avoid signal threshold violations(due to loss in long
path), use repeaters to boost signal strength at spec.
intervals.

This is a signal integrity question for board designers.
there are two types of termination schemes viz. series and
parallel termination. series termination is where a resistor
of small value ( rule of thumb 1/2 of characteristic
impedance  of the trace ) placed near the source ( near
driver). the parallel termination is a combination of two
resister ( rule of thumb twice the char. impedance f the
trace) placed near the destination ( input) where one
resistor connects the signal trace to the VCC and other
connects to the GNd.

a cdm clamp can be used at the receiver input to protect 
the circuitry form overshoot/ undershoot

if the input signal is asynchronous with the clock (state 
machine clock), then you need to double clock the same 
signal to synchronize with the state machine clock.

When signal transfer from one clock domain sequential to 
another clock domain sequential logic